Positioning control system for a machine that performs work on a moving part

ABSTRACT

A programmable and manually operable control system for controlling the position of a machine relative to a workpiece so the machine may perform work at various locations on the workpiece while the workpiece is moved by the conveyor. The system includes a pair of synchro resolvers which provide output signals indicative of the position of the machine relative to a datum position and a pair of synchro resolvers which provide output signals indicative of the position of the conveyor relative to the datum position. The outputs of the machine indicating resolvers provide the inputs to the conveyor indicating resolvers and the outputs of the conveyor indicating resolvers are compared with command signals that are generated by a continuously recycling counter which has been preset by signals from a memory so the displacement between selected locations on the workpiece and the machine is electrically measured without using differential mechanical gearing. The control system is arranged so the machine will move synchronously with the workpiece, independently of the workpiece, and synchronously with the workpiece while the machine is moving from one preprogrammed location to a new preprogrammed location on the workpiece.

United States Patent 1 Anger et al.

1 May 8, 1973 [54] POSITIONING CONTROL SYSTEM FOR A MACHINE THAT PERFORMS WORK ON A MOVING PART [75] Inventors: Ernest G. Anger, Wauwatosa; Giles J. Richards, Menomonee Falls; John F. Bloodgood, Fond du Lac; Roy J. Geiger, Cedarburg, all of Wis.

[52] U.S. Cl. ..318/257, 318/314, 318/341 [51] Int. Cl ..H02p 5/06 [58] Field of Search ..318/257, 314, 341

[56] References Cited UNITED STATES PATENTS 3,355,640 11/1967 Lewis et al ..318/257 X 3,439,246 4/1969 Moritz ..318/257 3,579,080 5/1971 Vollrath 318/257 X 3,500,160 3/1970 Sommer ...318/3l4 X 3,612,974 10/1971 Wolf ..318/257 Primary ExaminerBenjamin Dobeck Attorney- Harold J. Rathbun et al.

[57] ABSTRACT A programmable and manually operable control system for controlling the position of a machine relative to a workpiece so the machine may perform work at various locations on the workpiece while the workpiece is moved by the conveyor. The system includes a pair of synchro resolvers which provide output signals indicative of the position of the machine relative to a datum position and a pair of synchro resolvers which provide output signals indicative of the position of the conveyor relative to the datum position. The outputs of the machine indicating resolvers provide the inputs to the conveyor indicating resolvers and the outputs of the conveyor indicating resolvers are compared with command signals that are generated by a continuously recycling counter which has been preset by signals from a memory so the displacement between selected locations on the workpiece and the machine is electrically measured without using differential mechanical gearing. The control system is arranged so the machine will move synchronously with the workpiece, independently of the workpiece, and synchronously with the workpiece while the machine is moving from one preprogrammed location to a new preprogrammed location on the workpiece.

6 Claims, 10 Drawing Figures PAIENTEUHAY'mma v 3,732,474

SHEET 2 0F 6 500 KHZ REF FIG.2

PATENTEDKAY' 81915 SHEET 3 OF 6 TMHZ REF (500 HZ) U n 2 H H O Y 0 O O 5 5 OUTPUT E FB FF OUTPUT E CC-FF OUTPUT NAND N9 OUTPUT E REV-FF IL *1. 1 v

OUTPUT E REP NOR O3 OUTPUT E FFWD OUTPUT FRS FIG.3

PATENTEU W 81975 SHEET 5 OF 6 i m mvz E. m m souo w m mww m mm mm 2 312 m PATENTEDHAY sum ,732,474

SH'LEI E H? 6 REF VOLTS POSITIONING CONTROL SYSTEM FOR A MACHINE THAT PERFORMS WORK ON A MOVING PART This is a division of application Ser. No. 146,110, filed May 24,1971, now US. Pat. No. 3,686,556.

The present invention relates to positioning control, and more particularly to a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position.

In the field of positioning control, various systems have been proposed for moving a controlled member in accordance with instructions stored within a memory so that work may be automatically performed upon a workpiece. In these prior systems, the maximum range of movement of the controlled member is usually limited to a few feet and generally the workpiece is maintained stationary while work is performed by the controlled member. Thus the systems as heretofore known are not particularly suited to control the positioning of a machine which performs work at various positions along the entire length of the body of an automotive vehicle while the body is transported by a moving conveyor through a work station.

A technique commonly practiced in factories which manufacture or assemble mass-produced automotive vehicles requires that the components of the subassembliesfor a complete vehicle be assembled to each other while the components are carried by a suitable support that isv moved by a conveyor past the various work stations where parts are secured to each other to complete the subassembly. For example, the fabrication of a subassembly, called the body of the vehicle, is normally accomplished by accurately positioning the components on a fixture, called a body truck, and moving the body truck past work stations where the parts of the body are welded together. The welding of the parts is accomplished by welding guns which are manually moved to the desired positions along the body parts to secure the parts together by a series of spot welds which are sequentially formed as the gun is positioned at spaced locations along the body parts. While the manual formation of spot welds has proven satisfactory, it is objectionable in that it not only depends upon the skill of the gun operator to accurately locate the welds and to assure that the proper number of welds are made between the parts, but it also occasionally requires the operator to assume physically uncomfortable and exhausting positions to make the welds.

While it is apparent that the machine as controlled by the control system as will be hereinafter described may be readily modified to perform a variety of operations upon workpieces while the workpieces are moving along a predetermined path, the control system is described as controlling the positioning of a resistance welding gun to form spot welds between parts of an automotive vehicle body as the body parts are transported by a moving body truck along a conveyor line. One of the problems presented in synchronizing the operation of a machine with the position of parts carried on a conveyor is that, conventionally, the speed of the conveyor which moves the parts is not closely controlled. Another problem presented in using machines to perform workon body parts which are carried on a moving conveyor in an automotive vehicle factory is that to maximize production, it is imperative that the conveyor move continuously. This means that any malfunction of a machine which would require the conveyor to be stopped would be highly objectionable. One type of failure or malfunction which may occur in a resistance spot welding apparatus is the weld electrodes may be stuck to the parts which are being welded together. When this type of failure occurs and the apparatus is being manually operated, minimal difficulties result as the human operator merely moves along the line until the welding electrodes are freed from the body part. However, when this type of failure occurs in a machine controlled welding apparatus, more disasterous consequences may occur because of the capability of the machine to pull the parts from their position on the body truck or to mutilate the parts beyond use.

To successfully perform work upon a workpiece carried by a conveyor, a machine which performs the work must be capable of operating in several modes. In one mode of operation, the machine must be capable of moving upstream and independently of the conveyor to a position where it waits for a part to enter the work station and then move with the part to preprogrammed positions on the part where it performs its work as the part is moved through the work station. In another mode of operation, the machine must be capable of having its movements manually controlled when the conveyor is stationary. In another mode of operation, the machine must be capable of moving synchronously with the part as the part moves through the work station.

It is to be appreciated that while the control, as will be hereinafter described, is concerned with the positioning of a machine along a longitudinal axis relative to a part that is carried by a moving conveyor, a multiple axis controlof the machine, i.e., six axis control, may be readily obtained by duplicating the necessary components of the control for the longitudinal axis with. the exception that the synchro resolvers, which are used to synchronize the movement of the machine with the movement of the conveyor, are eliminated.

It is an object of the present invention to provide a control system for a machine which will automatically perform work on workpieces that are carried on a moving conveyor.

Another object is to provide a control system for a machine which will control the position of the machine relative to preselected positions on a part so the machine may perform work on the part while the part is moved by the conveyor.

A further object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means for electrically synchronizing and controlling the movement of the machine with respect to the movement of the workpiece.

An additional object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means for electrically synchronizing the movement of the machine with respect to the workpiece, with said synchronizing means including a first pair 'of synchro resolvers which provide an output indicative of the position of the machine relative to the datum position, a second pair of synchro resolvers which provide an output indicative of the position of the workpiece relative to the datum position, a means which is arranged to be energized by the output of the first pair of resolvers and provide an input to the second pair of resolvers and a means which is arranged to compare the outputs of the second resolvers with recycling command position signals and cause the command signals to correspond with the outputs of the second pair of resolvers when the machine is required to move synchronously with the workpiece along the path of movement of the workpiece.

A still further object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means for electrically synchronizing the movement of the machine with respect to the workpiece that includes a pair of synchro resolvers each of which provides an output indicative of the position of the machine relative to the datum position, a second pair of synchro resolvers each of which provides an output signal indicative of the position of the workpiece relative to the datum position, a means for causing the inputs of the second pair of resolvers to be energized by the outputs of the first pair of resolvers and a means which compares both the order of occurrence and the interval between the occurrence of the output signals of the second pair of resolvers and a command signal and provides an error signal which has a magnitude dependent upon the interval between the signals and a direction indication controlled by the order of occurrence of the signals.

A still further object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means for electrically synchronizing the movement of the machine with respect to the workpiece that includes a pair of synchro resolvers each of which provides an output indicative of the position of the machine relative to the datum position, a second pair of synchro resolvers each of which provides an output signal indicative of the position of the work piece relative to the datum position, a means for causing the inputs of the second pair of resolvers to be energized by the outputs of the first pair of resolvers and a means which compares both the order of occurrence and the interval between the occurrence of the output signals of the second pair of resolvers and a command signal and provides an error signal which has a magnitude dependent upon the interval between the signals and a direction indication controlled by the order of occurrence of the signals and to provide the control with a means which is manually operable to cause the machine to move independently of the signals.

Another object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means which provides a feedback signal that is indicative of the relative positions of the workpiece and the machine relative to the datum position, a means including a recycling counter which provides a command signal phase that is preset to be indicative of a preselected position on the workpiece at which the machine is to be positioned while the workpiece is moving relative to the datum position and a hold means responsive to the feedback signal for causing the output of the counter to correspond to the feedback signal during periods when the hold means is activated.

An additional object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means which provides a feedback signalthat is indicative of the relative positions of the workpiece and the machine relative to the datum position, a means including a counter which provides a command signal that is indicative of a preselected position on the workpiece at which the machine is to be positioned while the workpiece is moving relative to the datum position, a jog means for causing the machine to move at either of two selected speeds independently of the workpieces when the jog means is activated, said jog means including circuitry that is responsive to the feedback signal for causing the output of the counter to correspond to the feedback signal during periods when the jog means is activated and a means which will cause the movement of the machine to increase at a preselected rate when the jog means is actuated and to abruptly decrease when the jog means is deactivated.

A further object is to provide a control system for positioning a machine at desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means which provides a feedback signal that is indicative of the relative positions of the workpiece and the machine'relative to the datum position, a means including a counter which provides a command signal that is indicative of a preselected position on the workpiece at which the machine is to be positioned while the workpiece is moving relative to the datum position and a jog means for causing the machine to move independently of the workpieces when the jog means is activated, said jog means including circuitry thatis responsive to the feedback signal for causing the output of the counter to correspond to the feedback signal during periods when the jo'g means is activated.

Another object is to provide a control system for controlling the energization of an electric motor which drives a machine to desired positions along a workpiece while the workpiece is moving along a predetermined path relative to a datum position with a means which provides a feedback signal that is indicative of the relative positions of the machine and workpiece relative to the datum position, a means which provides a command signal that is indicative of a preselected commanded position on the workpiece at .which the machine is to be positioned, said feedback and command signals consisting of a predetermined voltage change which occurs at predetermined instants during each cycle of a reference wave and respectively varying in time during each cycle depending. upon the relative positions of the machine and workpiece from the datum position and the location of the desired position relative to the datum position, means for comparing both the order of occurrence and the interval between the occurrence of the voltage changes of the feedback and the command signal and providing an output signal pulse during each half cycle which has a width dependent upon the interval between said pulses and a polarity indicative of the order of occurrence of the pulses, and a deceleration means for controlling the direction of rotation and the speed of rotation of the motor in response to the polarity and width of the pulses, said deceleration means being arranged to exponentially increase the ratio between the width of the pulses and the energization of the motor as the width of the pulses decreases during periods when the machine is slowing down as the machine is approaching the commanded position.

Further objects and features of the invention will be readily apparent to those skilled in the art from the following specification and from the appended drawings illustrating certain preferred embodiments, in which:

FIG. 1 shows in block diagram form a control system embodying the features of the present invention.

FIG. 2 is a schematic and block diagram of the circuitry used to compare the outputs of the position detecting resolvers and the command position signal provided by the components in FIG. 1.

FIG. 3 is a graphical representation showing the time relationships of signals in the circuit shown in FIG. 2.

FIG. 4 is a schematic and block diagram of the circuitry used to cause the machine in FIG. 1 to operate in a hold position and/or ajogging mode of operation.

FIG. 5 is a schematic diagram of the circuitry used to control the energization and de-energization of a drive motor for the machine in FIG. 1 when the jogging mode of operation is initiated and terminated.

FIG. 6 is a schematic diagram of a circuit which controls the energization of the drive motors for the machine in response to the output signal from the comparator circuit in FIG. 1.

FIGS. 6A and 6B are graphs illustrating the change in the energization of the drive motor for a machine in FIG. 1 as the machine moves toward a commanded position.

FIGS. 6C and 6D are graphs with time as a reference, illustrating the manner in which a capacitor in FIG. 6 is charged in response to error pulses.

Referring now to the drawings, and more particularly to FIG. 1 thereof, the control system of the present invention is therein illustrated as controlling the position of a machine 10 relative to the position of a pair of workpieces l1 and 12, which represent parts of an automotive vehicle body, that are carried on a longitudinally movable fixture, known in automotive assembly plants as a body truck 13. In conventional practices, as followed in automotive assembly plants, a succession of spaced trucks 13 are continuously moved along a path dictated by a pair of spaced rails 14 past work stations where work is performed on the parts carried by the trucks. Each of the trucks 13, as used with the present system, has a block 15 secured at one of its longitudinal sides with an opening 16 accurately located in the block 15 relative to the workpieces l1 and 12. The opening 16 is located to receive a-pin 17 that projects upwardly from a longitudinally movable chain 18 which is moved by the truck 13 horizontally along a path parallel to the rails 14 in the direction indicated by the arrow 19 as the truck 13 moves from an upstream end 20 of the work station, wherein the machine 10 is located, to the downstream end 21 of the work station. The chain 18 is arranged so that as a truck 13 enters the upstream end 20 of the work station, the pin 17 will be projected upwardly, by a means not shown, into the opening 16 to cause the chain as well as the pin 17 to be moved by the truck 13 downstream to the end 21 whereat the pin 17 is retracted from the opening 16 in the block 15 as the truck 13 carryingthe fabricated workpieces 11 and 12 leaves the work station, so that the chain 18, including the pin 17 may be moved by a means, not shown, upstream to the upstream end 20 where it will be in a position to engage a block 15 on a subsequent truck 13, as the truck 13 enters the work station.

The machine 10 includes a base 22 that is movable along the parallel rails 23 along a path that is parallel and spaced from the path of movement of the truck 13. The .base 22 is moved by a lead screw 24 through a suitable travelling nut, not shown, which is secured to the base 22 and arranged to be driven by the lead screw 24. The lead screw 24 is rotated through a suitable speed reducing gear box 25 by an electric motor 26. A vertical stanchion 27, which is secured on the base 22, supports an arm 28. The arm 28 is supported by the stanchion 27 so that the arm 28 may move horizontally along a horizontal axis that extends vertically to the path determined by the rails 14 and rotate about its horizontal axis. Secured on the free end of the arm 28 is a pair of electrodes, indicated as 29, which are arranged to engage and spot weld the workpieces 11 and 12 together. The electrodes 29 are movable by a suitable mechanism 30 in an arcuate path along a vertical axis as well as an arcuate path that extends horizontally. The horizontal arm 28 is also movable along a vertical axis on the stanchion 27. Thus the movement provided by the base 22 along the axis dictated by the rails 23, the vertical, horizontal and rotational movement of the arm 28 about the stanchion 27 and the movement provided by the mechanism 30 on the end of the arm 28 about the horizontal and vertical axes, will permit electrodes 29 to move along six axes relative to the workpieces 11 and 12.

A system which will control the horizontal positioning of the machine 10 along an axis parallel to the movement of the body truck 13 and the workpieces 11 and 12 includes a memory 31 which is preferably of the retentive type so that information stored therein will not be lost in the event of a power failure. The memory 31, as used herein, is a commercially available type, and includes an array of bistable state magnet cores which are capable of being programmed to have information stored therein. The information which is stored in the cores of the memory 31 includes positional information which will dictate the desired positions of the welding electrodes 29 relative to the workpieces 1 l and 12, functional information which controls the operation of the welding electrodes, information which will control other mechanisms of the machine, such as operation solenoids and the like, and program information which will indicate that the programmed work for any particular type of parts 11 and 12, which may be mounted on the body truck, has been completed.

The operation of the control system is dictated by suitable circuitry within an operator control station module 32 which supplies input signals to a sequence control circuit module 33 and a hold-jog circuit module 34. While the control module 32 may be programmed to cause the control system to operatethe machine 10 in modes other than are herein described, for purposes of understanding of the operation of the circuits which will be later described, the control module 32 is described as providing suitable output signals which will cause the machine to operate in an automatic mode, an indexing mode, a teach and jogging mode and a mode designated as hold.

The control module 32, when programmed to cause the machine to operate in the index or automatic mode, will provide signal inputs to the sequence control module 33 which will cause the digital command information stored within the memory 31 to be read out through gates 35, 36 and 37 and be respectively supplied as input information to a coarse command counter 38, a fine command counter 39, circuits within a function module 40 and circuits within an end of program and miscellaneous function module 41. The counters 38 and 39 are 1,000 bit recirculating counters and receive a continuous train of 500 KHZ reference input pulses from a system timing module 42. When the continuous train of 500 KHZ, pulses is fed into the counters 38 and 39 and the counters 38 and 39 are reset by the reference input pulses and preset by the information from the memory 31, the train of 500 HZ pulses will appear at the output of the most significant bit of the counters 38 and 39 which will have a predetermined phase relationship with respect to a 500 HZ'reference input signal pulses and thereby in effect divide each cycle of the 500 HZ input signal into 1,000 distinct command positions.

A position responsive means which provides a signal indicative of the position of the machine 10 relative to a datum position 43, located equidistant between the ends 20 and 21, includes a coarse feedback resolver 44 and a fine feedback resolver 45. Similarly, a position responsive means which will provide a signal indicative of theposition of the pin 17 relative to the datum position includes a coarse feedback resolver 46 and a fine feedback resolver 47. Each of the resolvers 44-47 is a synchro type resolver and includes a rotatable shaft, a pair 'of input windings wound in spaced quadrature and an output winding that provides a cyclic output voltage signal which varies in phase relative to the phase of the voltage across its input windings with the angular position of the shaft when the input windings are respectively energized from an alternating current source by equal magnitude alternating voltages that are in quadrature.

The shaft of the coarse feedback resolver 44 is connected through a gear box 48 to be rotated by the lead screw 24 one complete revolution when the machine l'is moved twice the distance between the ends 20 and 21. The shaft of the fine feedback resolver 45 is connected through a gear box 49 to be rotated by the lead screw 20revolutions. for each revolution of the shaft of the coarse resolver 44. The shaft of the coarse feedback resolver 46 is connected through a gear box 50 to be rotated in response to the movement of the chain 18 one complete revolution when the pin 17 is moved twice the distance between the ends 20 and 21. Similarly, the shaft of the fine resolver 47 is connected through a gear box l'to be rotated in response to they movement of the chain 20 revolutions for each revolution of the shaft of the coarse resolver 46.

A sin/cos generator circuit module 52, which is controlled by the timing module 42, supplies one of the input windings of the resolvers 44 and 45 with a 500 HZ sine wave input that is in phase with the 500 HZ reference sine wave input to the counters 38 and 39 and the other of the pair of input windings of the resolvers 44 and 45 with a 500 HZ sine wave of equal amplitude, but lagging the reference sine wave by (cos). With this excitation, the outputs of the resolvers 44 and 45 will vary in phase relative to the reference sine wave with the position of their respective shafts. The 500 HZ sine wave output of the resolver 44 is supplied as an input through a lead 53 to one of the windings of the resolver 46 and is integrated by an integrator circuit module 54 and supplied to the other input winding of the resolver 46 as a 500 HZ sine wave of equal amplitude, but lagging in phase by 90 (cos) with the excitation voltage supplied by the lead 53. Similarly, the 500 HZ sine wave output of the resolver 45 is supplied as an input through a lead 55 to one of the pair of input windings of the resolver 47 and is integrated by a circuit module 56 and'supplied to the other input of the winding of the resolver 47 as a 500 HZ sine wave of equal amplitude but lagging in phase by 90 (cos) with the excitation voltage supplied by the lead 55. r I

The 500 HZ sine wave outputs from the resolvers 46 and 47 are respectively amplified, clamped and rectified by circuits within switch modules 57 and 58 to The output of the coarse command counter '38, hereinafter referred to as a coarse command signal CC, v

is a-logic l to 0 transition at the trailing edge of each cycle of the 500 HZ voltage wave. Thel ,to 0 signal 7 change can be made to occur at any one of -l,000 different instants during each cycle of the 500 HZ reference voltage wave so that the coarsecommand counter 38 can be programmed to provide 1,000 distinct coarse command signals for each revolution of the coarse resolver 44 or 46. Similarly, the fine command counter 39 can be programmed to provide 1,000 distinct command 1 to 0 logic signals, or fine command signals PC, for every 1/20 revolution of. the coarse resolver 44 or 46. Therefore, if it is assumed that the total distance between the ends 20 and 21 is 200 inches and both the machine 10 and the truck 13 are capable of moving 200 inches, then the relative range of movement between the workpieces 11 and 12 and the electrodes 29 will be 400 inches. Thus as the coarse command counter 38 is capable of providing 1,000 distinct coarse command signals over the entire range of movement (one revolu-tion of the coarse resolvers 44 and 46)which is 400 inches, and the fine command counter linear axis will have a resolution of 0.02 inches and the system has the capability of being programmed to 20,000 distinct command positions within the 400 inch range of relative movement between the machine and the truck 13.

As will be later described, the circuitry within the coarse comparator 59 compares the coarse feedback signal CFB with the coarse command signal CC and provides an output error signal to a switch module 61 which is dependent upon the order of occurrence and the time interval between the l to 0 change in the signals from the compared signals which will cause the motor 26 to be energized to rotate either in the forward or reverse directions, depending on the order of occurrence of the 1 to 0 signals at a predetermined rate when the time interval between the signals is greater than a preselected interval. Also, the fine comparator 60 compares the fine feedback signal FFB with the fine command signal FC and provides an output error signal to the switch module 61 which is dependent on the order of occurrence and the interval between the 1 to 0 change in the signals which it compares. The output error signal from the fine comparator 60 to the switch module 61 will cause the motor 26 to be energized to rotate in the forward or reverse directions depending upon the order of occurrence of the 1 to 0 signal changes of the compared signals at a rate dependent upon the magnitude of the interval between the signal change of the compared signals.

The output of the switch module 61 is supplied as an input to a deceleration module 62, which will be later described. The module 62 converts and modifies the output pulses from the switch module 61 to a positive or negative filtered DC. voltage which is supplied as an input to a servo-drive amplifier 63 which in turn controls the energization of the motor 26. If desired, the drive amplifier 63 may also be furnished with an input signal from a tachometer 64 that is driven by the motor 26 to limit the energization of the motor 26.

The motor 26, when energized, will rotate the lead screw 24 through the gear box 25 to move the electrodes 29 which are supported by the base 22 and rotate the shafts of the resolvers 44 and 45 in a direction which will reduce the error signals as detected by the comparators 59 and 60. When the electrodes 29 are in their commanded position relative to the workpieces 11 and 12, the 1 to 0 signal changes of the coarse feedback signal CFB and the coarse command signal CC will be in phase and the 1 to 0 signal change of the fine feedback signal FFB will be in phase with the fine command signal PC which will cause the switch module 61 to supply an in position signal to the logic circuitry within an end of motion module 65. The module 65 in response to' the in position input signal supplies a signal to the function module 40 which will initiate the operation of a weld sequence timer and cause the electrodes 29 to spot weld the workpieces l1 and 12 together. During the weld interval, when the spot weld is being formed, the workpieces 11 and 12 will be moving through the work station and the feedback outputs of the coarse and the fine resolvers 46 and 47 will be continuously changing. The fine comparator 60, in response to the changing fine feedback signal FFB, will provide an output through the circuits in the switch module 61 and the deceleration module 62,,

which causes the servo-drive amplifier 63 to provide the motor 26 with an energization that is exactly sufficient to move the machine 10 synchronously with the truck 13. The synchronous movement of the machine 10 causes the coarse and fine resolvers 44 and 45- to supply a changing input to the coarse and fine resolvers 46 and 47 which in turn reduces the changing coarse and fine feedback signal input to the comparators 59 and 60 so that the welding electrodes 29 remain in their programmed position as they are forming a spot weld between the workpieces 11 and 12.

The function module 40, at the end of the weld interval, will supply an input through the lead 66 to the sequence control module 33 which causes the sequence control module 33 to sequence the memory 31 and open the gates 35-37 to reprogram the coarse and the fine command counters 38 and 39, and the function module 40, so that the command counters 38 and 39 provide output command signals which will require the machine 10 to move to a new preprogrammed position relative to the workpieces 11 and 12. The coarse and fine comparators 59 and 60 in response to the changed coarse and fine command signal will provide an output signal which will cause the motor 26 to be energized to reduce the error signal in a manner previously described as the machine 10 moves to its newly commanded position relative to the workpieces 11 and 12.

At the end of the program, that is, when all the required spot welds have been made between the parts 11 and 12 at the positions dictated by the information stored within the memory 31, the end of program module 41 will supply a signal through a lead 67 to the switch modules 57 and 58. Also at the end of the program, the memory 31 will supply suitable inputs through the gates 35 and 36' to the coarse and fine command counters 38 and 39 which will cause the counters to supply coarse and fine command signals which will require the machine 10 to move upstream to its start position at the end 20 where it will await the entry of a subsequent truck 13 carrying unassembled workpieces into'the work station. The circuitry within the switch modules 57 and 58 is arranged so that a signal input from the module 41 will cause the switch modules 57 and 58 to respond to the outputs of the resolvers 44 and 45 instead of the'outputs from the resolvers 46 and 47 and permitthe machine 10 to move independently of the chain 18 upstream to the end 20. During the movement of the machine 10 to the end 20, the truck 13 carrying the assembled workpieces will continue to move toward the end 21. The pin 17 is disengaged from the opening 16 when the truck 13 leaves the work station at the end 21, so that the chain 18 may be moved upstream and position the pin 17 at the end 20 where it will engage the opening 16 in a subsequent truck 13 as the subsequent truck 13 enters the work station.

The foregoing operation constitutes a description of the operation of the control system when the control module 32 is programmed so that the machine 10 will operate in the automatic mode. The indexing mode of operation is provided in the control system to check the information stored within the memory 31 during periods when the conveyor which moves the body truck 13 is stopped. The program within the memory 31 may be checked by merely pressing a button in the control module 32 which will cause the machine 10 to move from one preprogrammed position to its next programmed position and maintain its position until the indexing button is again depressed, which will sequence the memory 31 one step and require the machine 10 to move to a new position. Thus the machine 10 may be sequenced through its programmed steps to determine if the information within the memory 31 corresponds to a program which will locate the spot welds between the workpieces 1 1 and 12 at their desired locations.

A hold mode of operation is included in the control system to minimize damages which could occur in event an emergency should occur while the machine 10 is operating in its automatic mode and it becomes necessary to stop the conveyor line which moves the trucks 13. The hold mode of operation may be initiated at any time by activating a suitable hold switch in the control module 32. If the machine 10 is moving toward a new position on the workpieces 11 and 12, when the hold mode of operation is initiated, the coarse and fine command signals will be reset to correspond to the coarse and fine feedback signals, in a manner to be later described in detail, and the movement of the machine 10 will be synchronized with the movement of the conveyor as the conveyor coasts to a stop.

The initiation of the hold switch will cause the holdjog module 34 to supply a signal for a brief time interval, i.e., 380 milliseconds, to the comparators 59 and 60 which will block the operation of the comparators 59 and 60 and cause the comparators 59 and 60 to supply a zero output error signal which will permit the motor 26 to decelerate. During the 380 millisecond time interval, the Hold-jog module 34, in response to feedback signals from the resolvers 46 and 47, will supply input signals to the counters 38 and 39 which will preset the counters 38 and 39 when the coarse and fine feedback signals change from 1 to so that the coarse and the fine command signals will be in phase with the coarse and the fine feedback signals. The presetting of the counters 38 and 39 will occur approximately 190 times during the 380 millisecond interval after which the comparators 59 and 60 will cause the motor to, be energized to, an extent necessary to cause the machine to move synchronously with the truck 13 asthe truck 13 coasts to a stop.

The teach mode of operation is included in the control system to permit the machine 10 to be manually controlled in its movement to a variable number of discreet positions relative to the workpieces 11 and 12 to which the machine 10 can be later caused to move in automatic play-back mode. The' operators control module 32 is provided with a suitable switch which will cause the system to operate in the automatic or teach mode and job switches which, when operated, will energize the motor 26 to jog machine 10 in either a fast or slow jogging speed. The teach mode of operation may be initiated by activating the teach and jog switches in the control module 32. When the teach and jog switches are activated, the machine 10 will move to a desired position on the workpieces 11 and 12 and the jog-hold circuit will operate in a manner which will be later described. During the movement of the machine 10 in thejogging mode, the coarse and fine command signals will be preset to correspond to the coarse and fine feedback signals. When the machine 10 is in its desired position, and a suitable second switch within the control module 32 is activated, the information which is stored within the coarse and fine counters 38 and 39 will be transferred into one bank of the memory 31. When the machine 10 is again jogged to a new position, the coarse and fine command signals again will be preset to correspond to the coarse and fine feedback signals so that the information which correspondsto the new position may be transferred out of the command counters 38 and 39 into the next sequenced bank of the memory 31. The movement of the machine 10 to any number of desired locations is repeated until the desired number of spot weld locations are recorded in the memory 31.

When the jog switches are operated in the control module 32, the jog hold circuit 34 will supply a suitable input to the switch module 61 which will cause the drive motor 26 to rotate in either the forward or reverse direction at either a fast or slow speed, depending upon the actuation of the jog switches. The circuitry within the jog-hold module 34 is arranged so that the rotation of the motor 26 progressively increases to the selected jog speed when the jog switch is initially actuated and abruptly reduced when the jog switch is deactivated to aid in the accurate positioning of the electrodes 29 on workpieces 11 and 12. I p

The circuits as shown in the drawings includes a plurality of solid state logic units designated as NANDS, ANDS, NORS and JK type flip flops, all of which are well known to those skilled in the art, and provide outputs in response to inputs as follows. A NAND provides a Boolean logic operation which yields a logic 0 output when all of its logic input signals are logic 1 and a logic 1 output when any of its logic input signals are logic 0. An AND provides a Boolean logic operation which yields a logic 1 output when all its logic input signals are logic 1 and a logic 0 output when any of its logic input signals are logic 0. A NOR provides a Boolean logic operation which yields a logic 1 output when all of its logic input signals are logic 0 and a logic O'output when any of its logic input signals are logic 1. A flip flop is a circuit that has two stable states and the capability of changing from one state to another with 'the application of a control signal and remaining in that state after removal of the signals. A J K flip flop is aflip flop having two inputs designated as J and K and a toggle designated as T which, upon a logic 1 to 0 change at its toggle T with a logic 1 on its 1 input and a logic 0 on the K input, will set the flip flop in the ON state and with a logic 0 on its J input and a logic 1 on the K input will set the flip flop in its OFF state. The JK flip flops as used herein also include a set input designated by a letter S which is not controlled by the signals appearing at the toggle T and will switch the flip flop to its ON state in response to a logic 0 signal at its set input S. A JK flip flop, when in the ON state, will supply a l at its E output and a 0 at its E output. When in the OFF state, a JK flip flop will supply a O at its E output and a l at its E output.

The coarse comparator circuit, shown in FIG. 2 and designated as 59 in FIG. 1, includes a coarse command flip flop CC, a feedback flip flop FB, a reset flip flop RS, a flip flop FWD designated as a forward flip flop, a flip flop REV designated as a reverse flip flop, a flip flop SS designated as the single shot flip flop, NANDS Nl-Nl0, ANDS Al-AZ, and a NOR 01. The coarse comparator circuit receives input signals from the coarse command counter 38, the resolver 46 and the timing module 42, illustrated in FIG. 1, as are typically illustrated by the curves in FIG. 3. The coarse command counter provides the coarse command signal CC, the resolver 46 provides the coarse feedback signal CFB and the timing module 42 provides the signals 500 KHZ, REF and lMHZ. The forward FWD and reverse REV flip flops have their outputs E andEconnected to supply inputs to ANDS A3-A6 which in turn provide inputs to a pair of NORS 02 and 03.

The fine comparator circuit includes a flip flop FFWD which is designated as the fine forward flip flop, a flip flop FREV which is designated as the fine reverse flip flop, a flip flop FRS which acts as a fine reset flip flop, and NANDS which are designated as N11-N20. The fine comparator circuit receives inputs from the fine command counter 39, the resolver 47 and the timing module 42 shown in FIG. 1. The fine command counter provides the fine command signal FC, the resolver 47 provides the fine feedback signal FFB and the module 42 provides the signals 500 KHZ and lMHZ. The signals FWP and REP are synchronized with the fine command signal FC.

COARSE COMPARATOR CIRCUIT The NAND N7 has an input 1 connected to the signal source REF and an input 2 connected to an output E of the flip flop RS. The flip flop IRS is turned ON by a input from the 500 KHZ signal on its input S. In its ON state, the flip flop RS supplies a 1 signal at its output E. The source REF supplies a 0 signal pulse that has a 500 nanosecond duration at a rate of 500 cycles per second. Thus every 500 cycles the output of the NAND N7 switches to provide a 500 nanosecond 0 to 1 signal pulse which is inverted by a NAND N8 and supplied as a l to 0 input to the inputs S of the flip flop CC and the flip flop FB respectively, so the flip flops CC and F8 are turned ON and respectively supply a 1 signal at their outputs E and a 0 signal at their outputs E. The flip flop CC has its toggle T connected to receive a coarse command input signal CC and is switched to an OFF state upon a l to 0 change in the signal CC. Similarly, the flip flop FB has its toggle connected to receive the coarse feedback signal CFB and is switched to an OFF state upon a 1 to 0 change in the signal CFB. The difference in time of occurrence of a l to 0 signal change of the coarse command signal CC and the coarse feedback signal CFB will provide an error signal which is indicative of both the direction and the distance which the coarse feedback resolver 46 must be rotated to reduce the error signal.

If the machine 10 is positioned so that the coarse feedback signal CFB changes from 1 to 0 prior to a l to 0 change in the coarse command signal CC, the control will operate to rotate the resolver 46 in a direction to reduce the error signal which, for purposes of description, is designated as a reverse direction REV. Similarly, if the coarse command signal CC changes from 1 to 0 prior to a change of l to 0 of the coarse feedback signal CFB, the control will operate to reduce the error signal and drive the resolver 46 in a forward direction FWD. In FIG. 3, the curves indicate the signals appearing at the inputs and outputs of the designated solid state components relative to a train of 500 nanosecond O pulses on a 500 cycles per second reference wave REF, when the control is programmed so the coarse feedback signal CFB changes from 1 to 0 prior to a change of l to 0 of the coarse command signal CC.

The l to 0 signal change of the coarse feedback signal CFB to the toggle T of the flip flop FB causes the flip flop FB to switch OFF and a 1 signal to appear at its output Eand a 0 signal at its output E. The 1 signal at output Eof the flip flop FB is supplied to an input 2 of the NAND N3, an input 1 of the NAND N5 and an input 3 of the AND A2. The 0 signal at output E of the flip flop FB is supplied to the J input of the flip flop REV, an input 2 of the AND Al, and an input 2 of the NAND N1. The NAND N3 through its input 1 also receives an input of 1 from the output E of the flip flop CC which remains in its ON state because the coarse command signal CC on its toggle T has not changed from 1 to 0. Thus as both inputs 1 and 2 of the NAND N3 are 1, the output of the NAND N3 switches to 0. The 0 output of the NAND N3 is inverted by a NAND N4 and is suppliedas a l to the K input of the flip flop REV to condition the flip flop REV to switch to an OFF state upon the receipt of a 1 to 0 signal change at its toggle T input. The AND A2 also receives a 1 signal at its input 2 from the flip flop RS output E and a 1 signal at its input 1 from the output E of the flip flop CC. As all of the inputs to the AND A2 are now 1, it switches its output to supply a 1 input to the NOR 01 which switches its output from 1 to 0.

The output of the NOR 01 is supplied as a 1 to 0 input signal change to the toggle T and the K input of the flip flop SS. The flip flop SS, in respons'eto the 1 to 0 output signal change of the NOR 01, switches to an OFF state so that a 0 signal appears at its output E and a 1 signal appears at its output E. The 1 to 0 signal change at the output E of the flip flop SS is inverted by the NAND N9 and supplied as a 0 to 1 signal input change to the toggles T of the flip flops FWD and REV.

During the interval when the flip flop SS is switched ON and its output E provides a 0 signal, the NAND N10 supplies a 1 signal to the input S of the flip flop. SS so that the flip flop SS is conditioned to switch to an OFF state upon the receipt of a 1 to 0 input signal change at its toggle T and its input K. The switching of the flip flop SS to an OFF state causes the signal at its output E to change from O to 1. This 0 to 1 signal change is delayed in its transmission to the input of the NAND N10 by a capacitor C1 and a resistor R1 so that the NAND N10 continues to supply a 1 signal to the input S of the flip flop SS after the flip flop SS has switched to an OFF state. After a fixed time delay, as determined by the RC constants of the resistor R1 and the capacitor C1, the charge on the capacitor C1 increases to a value which causes the NAND N10 to switch and supply a 0 input signal to the input S of the flip flop SS. The 0 input signal to the input S of the flip flop SS causes the flip flop SS to switch to an ON state and the output of the NAND N9 to switch from 1 to 0. The output of the NAND N9 is connected to the toggles T of the flip flops FWD and REV. Thus if the coarse command signal CC has not changed from 1 to 0 prior to the l to 0 signal change from the NAND N9, the flip flop FWD will remain ON and the flip flop REV will switch to an OFF state because of the 1 input signal at its K input and supply a 1 signal at its output Eand a signal at its output E.

As shown in FIG. 3, subsequent to the switching OFF of the flip flop REV and prior to the receipt of the signal change from the signal source REF, the coarse command signal CC changes from 1 to 0.

The l to 0 change of the coarse command signal CC to the toggle T of the flip flop CC causes the flip flop CC to switch OFF so that a 1 signal appears at its output E and a 0 signal at its output E. The 1 signal at the output Eof the flip flop CC is supplied to the input 2 of the NAND N which also receives a 1 input from the flip flop FB at its input 1 so that the NAND N5 is conditioned to switch when the 500 KHZ signal at its input 3 switches to 1. When all of the inputs 1, 2 and 3 of the NAND N5 are 1, its output switches to 0. The 0 output of the NAND N5 is inverted by the NAND N6 and supplied as a 1 to the K input of the flip flop RS which switches to an OFF state upon the receipt of a subsequent 1 to 0 signal change to its toggle T in the lMHZ signal. The flip flop RS when in an OFF state switches the flip flops CC and FE to their ON states and supplies a 0 signal to the input 2 of the AND 2 which causes the output of the AND A2 to switch from 1 to 0. The 0 output of the AND A2 causes the output of the NOR 01 and the input to the toggle T of the flip flop SS to change from O to 1 to condition the flip flop SS for switching from its ON to its OFF state when the signal at its toggle T again switches from 1 to 0 as previously described. The 1 from the 500 KHZ signal, which caused the NAND N5 to switch and supply a 0 output signal, is also supplied to the input S of the flip flop RS. Therefore when the 500 KHZ signal switches from 1 to O subsequent to the switching of the NAND N5, the flip flop RS will switch to its ON state.

Summarizing the foregoing, the switching of the flip flop PE in response to the l to 0 change in the coarse feedback signal CFB causes a l to be supplied to the K input of the flip flop REV and a 1 to 0 signal change to be supplied to the toggle T of the flip flop SS. The flip flop SS, resistor R1, capacitor C1 and the NAND N10 function as a single shot circuit and after a fixed time delay provide a l to 0 signal change to the toggles T of the flip flops FWD and REV. If the time delay provided by the single shot circuit is less than the time interval of the error signal, e.g., the interval between the 1 to 0 change in the coarse feedback signal CFB and the 1 to 0 changein the coarse command signal CC, the l to 0 signal change to the toggle T of the flip flop FWD will not change the ON state of the flip flop FWD because of the continuing O that is supplied by the output E of the flip flop CC to the input K of the flip flop FWD. The l to 0 signal change to the toggle T of the flip flop REV however causes the flip flop REV to switch OFF because of the 1 input to its K input. The flip flop REV when OFF supplies a O at its output E and a 1 at its output E and remains OFF as long as the duration of the error signal is greater than the fixed time delay provided by the single shot circuit.

The ANDS A3-A6 and the NORS 02 and 03 func tion as the switch 61 in FIG. 1 as follows. The outputs E of the respective flip flops FWD and REV are respectively connected to the inputs 1 of ANDS A3 and A5. The output E of the flip flop FWD is connected to an input 2 of an AND A4 and an input 1 of an AND A6. The output E of the flip flop REV is connected to an input 1 of an AND A4 and an input 2 of an AND A6.

The ANDS A3 and A4 have their outputs connected to the inputs 1 and 2 of a NOR 02 which has its output connected through a digital to analog converter in the deceleration module 62 in FIG. 1 to control the energization of a motor 26 in a manner which will drive the position resolvers 44 and 45 in the forward direction. Similarly, the ANDS A5 and A6 have their outputs connected to the inputs 1 and 2 of a NOR 03 which has its output connected through the deceleration module 62 to control the energization of a motor 26 in a manner which will drive the position resolvers 44 and 45 in a reverse direction. When both flip flops FWD and REV are ON, the 1 signals appearing at their respective outputs E will appear as a 1 signal at the inputs of the respective ANDS A4 and A6 so the ANDS A4 and A6 are respectively controlled by signals appearing at their inputs 3 during fine positioning, as will be later described. Further, when both flip flops FWD and REV are ON, the 0 signals appearing at their respective outputs Ewill cause the ANDS A3 and A5 to have 0 outputs which permit the NORS 02 and 03 to be controlled by the outputs of the ANDS A4 and A6.

The flip flop REV, when in an OFF state, supplies a 0 signal at its output E and a 1 signal at its output E The 0 signal at the output E thereby blocks the switching of the ANDS A4 and A6 in response to the signals from the fine positioning control, as will be later described. The 1 signal from the output Eof the flip flop REV is supplied to an input 1 of the AND AS which also receives a signal at its input 2 from the signal source REP. The source REP supplies a signal that is 1 during 20 percent of each cycle of the 500 cycle/sec reference wave and 0 during the remainder of each cycle. Thus the NOR 03 will have a 0 output for 20 percent of the time and energize the motor 26 to drive the motor 26 in the reverse direction to reduce the time duration of the error signal.

FINE COMPARATOR CIRCUIT p The solid state logic units in the fine comparator cit} cuit 60 will exist inthe following states when the fine comparator circuit 60 is reset. The flip flop the f flip flop 'FREV and the flip flop FRS will be 0N and provide a logic l at their respective E terminals and a logic 0 at their E terminals. The fine command signal FC and the fine feedback signal FFB will each provide a logic 1 signal to the fine comparator circuit 60. The 1 signal from the fine command signal FC is supplied to the toggle T of the flip flop FFWD and causes the NAND N15 to have a 0 output which is inverted by the NAND N16 and supplied as a 1 to the K input of the flip flop FREV. The logic 1 from the fine feedback signal FFB, which is supplied to thetoggle T of the flip flop FREV, causes the NAND N19 to have a 0 output which is inverted by the NAND N20 and supplied as a 1 to the K input of the flip flop FFWD. The 0 output at the E output of the flip flop FFWD is supplied to the input 2 of the NAND N11 and to the 1 input of the NAND N17 so that the NANDS N11 and N17 will have a continuing 1 output. The 0 output at the Eoutput of the flip flop FREV is supplied to an input 3 of the NAND N17 and an input 2 of the NAND N13 so that the NANDS N13 and N17 provide a continuing 1 output. The continuing 1 outputs from the NANDS N11 and N13 are inverted by the NANDS N12 and N14 respectively and supplied to the inputs 3 of the ANDS A4 and A6 respectively, so that the NORS 02 and 03 have a continuing 1 output. The output E of the flip flop FRS is supplied as a 1 to the inputs S of the flip flop FFWD and the flip flop FREV. During the operation of the fine comparator circuit 60, the ANDS A3 and A supply a continuous 1 to the inputs 1 of the NORS 02 and 03 respectively.

If the control is programmed so that the fine feedback signal FFB changes from 1 t0 0 prior to a change from 1 to O in the fine command signal FC, the control will operate to rotate the fine feedback resolver in a direction to reduce the error signal which, for purposes of description, is designated as the reverse direction. Similarly, if the signal from the fine command signal FC changes from 1 to 0 prior to a change of 1 to O in the fine feedback signal FFB, the control will operate to reduce the error signal and drive the fine feedback resolver in a forward direction. In FIG. 3 the curves indicate the signals appearing at the inputs and outputs from the sources indicated and the designated solid components when the machine 10 is positioned so that the fine feedback signal FFB changes from 1 to 0 prior to a change of l to O of the fine command signal FC. The continuing 1 fine command signal through the NANDS N and N16 causes a 1 signal input to be present at the K input of the flip flop FREV so that the change of 1 to 0 in the fine feedback signal FFB, at the toggle T of the flip flop FREV, causes the flip flop FREV to switch OFF and supply a 0 signal at its E output and a 1 signal at its Eoutput.

The l to 0 change of the signal from the fine feedback signal FFB also causes the NAND N19 to supply a l to an input 1 of the NAND N20. However, the NAND N20 continues to supply a 1 to the K input of the flip flop FFWD as the NAND N20 now receives a O at its input 2 from the E output of the flip flop FREV. The 1 at the output E of the flip flop FREV is supplied to an input 3 of the NAND N17 and an input 2 of the NAND N13. The output of the NAND N17 does not switch in response to the l at its input 3 because it continues to receive a 0 at its input 1 from the output Eof the flip flop FFWD so that the flip flop FRS remains in its ON state. The l to the input of the NAND N13 permits the state of the NAND N13 to be controlled by the signals from the source REP, which, as shown in FIG. 3, switches from a 0 to 1 72 prior to the switching of the signal from the fine command signal FC from I to 0 so that the signal from the source REP is 1 during 20 percent of each cycle of the fine command signal FC. Thus 72 prior to the signal change in the fine command signal FC, the NAND N13 has a l on both of its inputs 1 and 2 and thereby supplies a 0 input to the NAND N14 which in response thereto supplies a l to the input 3 of the AND A6. As previously described, the AND A6 also receives a l at its inputs 1 and 2 from the E outputs of the flip flops FWD and REV. Thus the output of the AND A6 switches to a 1 which causes the NOR 03 to supply a 0 signal to the deceleration module 62 which will control the energization of a motor 26 in a manner which will drive the position resolvers 44 and 45 in a reverse direction to reduce the error signal. As

shown in FIG. 3, subsequent to the change of the signal from 0 to l of the source REP, the fine command signal FC switches from 1 to 0. The l to 0 change of the fine command signal PC, which is supplied to the toggle T of the flip flop FFWD, causes the flip flop FFWD to switch so that a 1 signal appears at its outputE and a 0 signal at its output E.

The 1 to 0 change in the fine command signal FC also causes the NAND N15 to supply a l to the input 1 of the NAND N16. However, the NAND N16 continues to supply a l to the K input of the flip flop FREV as the NAND N16 now receives a 0 at its input 2 from the E output of the flip flop FFWD. The 1 at the output Eof the flip flop FFWD is supplied to an input 1 of the NAND N17 and an input 2 of the NAND N11 so that the NAND N17 now receives a 1 at each of its inputs 1 and 3 and is conditioned to be switched by the 500 KHZ signals. The 500 KHZ signal is supplied to both the input 2 of the NAND N17 and the input S of the flip flop FRS. Thus during the half cycle when the 500 KHZ signal is 1, the input S of the flip flop FRS will be 1 and the output of the NAND N17 will be 0. The NAND N18 inverts the 0 output of the NAND N17 and supplies a l to the K input of the flip flop FRS which switches to an OFF state when the signal at its toggleT from the lMHZ signal switches from 1 to 0. The switching to the ON state of the flip flop FRS causes the signal at its E output to change from 1 to 0 and is supplied to the input S of both the flip flops FFWD and FREV. The flip flops FFWD and FREV in response to the O signals at their inputs S switch to an ON state and respectively supply a 1 to the inputs 2 of the NANDS N16 and N20 so that the NANDS N16 and N20 now supply a 0 to the K inputs of the flip flops FFWD and FREV. The flip flops FFWD and FREV when in the ON state also supply a O to the inputs 1 and 3 of the NAND N17 which in response thereto through NAND N18 supplies a 0 to the input K of the flip flop FRS which causes the flip flop FRS to remain in its ON state after it is turned ON by a 0 pulse at its input S from the 500 KHZ signal on the subsequent change of the lMHZ signal at its toggle T. Thus the flip flops FFWD, FRS, and FREV are all in the ON state so that a subsequent change in the fine feedback signal FFB and the fine command signals from O to 1 will cause the NANDS N20 and N16 to respectively supply a l to the inputs K of the flip flops FFWD and FREV and restore the circuit to its reset state as previously described.

In view of the foregoing, it is obvious that if the machine 10 is positioned so that the coarse command signal CC changes from 1 to 0 prior to a l to 0 change in the coarse feedback signal CFB, the control will operate to rotate the resolvers 44 and 45 in a direction to reduce the error signal which, for purposes of description, is designated as the forward direction FWD, in a manner which may be summarized as follows. The flip flop CC will switch OFF in response to the l to 0 change in the coarse command signal CC and cause a l to be supplied to the K input of the flip flop FWD and a l to 0 signal change to be applied to the toggle of the flip flop SS. The flip flop SS, resistor R1, capacitor C1 and the NAND N10 function as a single shot circuit and after a fixed time delay provide a 1 to 0 signal change to the toggles T of the flip flops FWD and REV. If the time delay provided by the single shot circuit is less than the time delay interval of the error signal, e.g., the interval between i to change of the coarse command signal and the l to 0 change in the coarse feedback signal CFB, the l to 0 change to the toggle of the flip flop REV will not change the ON state of the flip flop REV because of the continuing 0 that is applied by the output E of the flip flop F8 to the input K of the flip flop REV. The l to 0 signal change to the toggle of the flip flop FWD however causes the flip flop FWD to switch OFF because of the 1 input to its K input. The flip flop FWD when OFF supplies a 0 at its output E and a l at its output E and remains OFF as long as the duration of the error signal is greater than the fixed time delay provided by the single shot circuit.

The flip flop FWD when in the OFF state, supplies a 0 signal at its output E and a 1 signal at its output E. The 0 signal at the output E thereby blocks the switching of the ANDS A4 and A6 in response to the signals from the fine positioning control. The 1 signal at the output E of the flip flop FWD is supplied to the 1 input of the AND A3 which also receives a signal at its input 2 from the signal source FWP. The source FWP supplies a signal that is 1 during 20 percent of each cycle of the 500 cycle reference wave after the coarse command signal CC changes from 1 to 0, and 0 during the remainder of the cycle. Thus the NOR 02 will have a 0 output for 20 percent of the time and energize the motor 26 to drive the motor 26 at a constant speed in the forward direction to reduce the time duration of the error signal.

If the control is programmed so that the signal from the fine command signal FC changes from 1 to 0 prior to a change of l to 0 in the fine feedback signal FFB, the control will operate to reduce the error signal and drive the fine feedback resolver in a forward direction.

The l to 0 change of the signal from the fine command signal FC also causes the NAND N to supply a l to an input 1 of the NAND N16. However, the NAND N16 continues to supply a 1 to the K input of the flip flop FREV as the NAND N16 now receives a 0 at its input 2 from the E output of theflip flop FFWD. The 1 at the output E of the flip flop FFWD is supplied to an input 1 of the NAND N17 and an input 2 of the NAND N11. The output of the NAND N17 does not switch in response to the 1 at its input 1 because it ontinues to receive a O at its input 3 from the output E of the flip flop FREV so that the flip flop FRS remains in its 0N state. The 1 to the input of the NAND N11 permits the state of the NAND N1 1 to be controlled by the signals from the source FWP which exists as a l for 72 after the fine command signal FC switches from 1 to 0 so that the signal from the source FWP is 1 during 20 percent of each cycle. Thus during an interval of 72 after the fine command signal has change to 0, the NAND N11 has a l on all of its inputs and thereby supplies a l to the input 3 of the AND A4. As previously described, the AND A4 also receives a l at its inputs 1 and 2 from the E outputs of the flip flops FWD and REV. Thus the output of the AND A4 switches to a l which causes the NOR 02 to supply a 0 signal to the deceleration circuit 62 which will control the energization of a motor 26 in a manner which will drive the position resolver 45 in a forward direction to reduce the error signal. As shown in FIG. 3, subsequent to the change of the signal from 1 to 0 of the source FWP, the

fine feedback signal FFB switches from i to 0. The 1 to 0 change of the fine feedback signal FFB, which is supplied to the toggle T of the flip flop FREV, causes the flip flop FREV to switch so that a 1 signal appears at its output E and a 0 signal at its output E.

The 1 to 0 change in the fine feedback signal FFB also causes the NAND N19 to supply a l to the input 1 of the NAND N20. However, the NAND N20 continues to supply a l to the K input of the flip flop FFWD as the NAND N20 now receives a O at its input 2 from the E output of the flip flop FREV. The 1 at the output E of the flip flop FREV is supplied to an input 3 of the NAND N17 and an input 2 of the NAND N13 so that the NAND N17 now receives a 1 at each of its inputs 1 and 3 and is conditioned to be switched by the 500 KHZ signals. The 500 KHZ signal is supplied to both the input 2 of the NAND N17 and the input S of the flip flop FRS. Thus during the half cycle when the 500 KHZ signal is l, the input S of the flip flop FRS will be 1 and the output of the NAND N17 will be 0. The NAND N18 inverts the 0 output of the NAND N17 and supplies a l to the K input of the flip flop FRS which switches to an OFF state when the signal at its toggle T from the. lMHZ signal switches from 1 to 0. The switching to the OFF state of the flip flop FRS causes the signal at its E output to change from i to 0 and is supplied to the input S of both the flip flops FFWD and FREV. The flip flops FFWD and FREV in response to the 0 signals at their inputs S switch to an ON state and respectively supply a l to the inputs 2 of the NANDS N16 and N20 so that the NANDS N16 and N20 now supply a 0 to the K inputs of the flip flops FFWD and FREV. The flip flops FFWD and FREV when in the ON state also supply a 0 to the inputs 1 and 3 of the NAND N17 which in response thereto through NAND N18 supplies a O to the input K of the flip flop FRS which causes the flip flop FRS to remain in its ON state after it is turned ON by a 0 pulse at its input S from the 500 KHZ signal on the subsequent change of the l to 0 of the l MHZ signal at its toggle T. Thus the flip flops I the NANDS N20 and N16 to respectively supply a 1 m g the inputs K of the flip flops FFWD and FREV so as to restore the circuit to its reset state, as previously described.

Thus when the interval between the occurrence of the coarse command and feedback signals is greater than the time interval as dictated by the single shot circuit that includes the flip flop SS, the motor 26 will be energized with constant current to operate either in the forward or the reverse directions because of the 20 per cent ON time signal pulses provided by the sources FWP and REP. The cross-over at which the control of the energization of the motor 26 is transferred from a control by the coarse feedback signal to the fine feedback signal occurs when the time interval between the coarse feedback and command signals is less than the time interval as dictated by the switching of the single shot circuit, including the flip flop SS. If the 'l to 0 signal changes in the coarse feedback and coarse command signals CFB and CC occur before the single shot circuit, including the flip flop SS, times out, a 0 will be present at the E outputs of the flip flops CC and FE before the signals at the toggles T of the flip flop FWD and REV changes from 1 to in response to the change in the output of the NAND N10, as previously described. The 0 at the E output of the flip flops CC and FE respectively will cause the K inputs of the flip flops REV and FWD respectively to be 0 when the signal input to the respective toggles changes from I to 0 so that neither of the flip flops FWD or REV will switch OFF to cause the motor to be energized.

The flip flops FWD and REV, when in the ON state, will permit the ANDS A4 and A6 to be controlled by the signals in the fine comparator circuit. The crossover from the control in response to the coarse feedback signal to the fine feedback signal is made to occur when the linear axis is approximately 5 inches from the desired position, or where the coarse error is equivalent to 12 coarse counts by the interval provided by the timing circuit including the flip flop SS. During positioning in response to the coarse error signal, the ANDS A3 or A5 will cause the deceleration module 62 to be supplied with a signal that is ON 20 percent of the time and OFF 80 percent of the time, regardless of the magnitude of the position error. When the control is switched to respond to the fine feedback signal, the sources FWP and REP will cause the ANDS A4 or A6 to supply the deceleration module 62 with a signal that is on 20 percent of the time and OFF 80 percent of the time. Thus the energization of the motor will not change during cross-over from positioning in response to the coarse error signal to positioning in response to the fine error signal. When the fine error signal becomes less than 200 counts, the deceleration module 62 will cause the energization of the motor 26 to be progressively decreased in response to a progressively decreasing fine error signal as the machine moves into its preprogrammed position relative to the workpieces 11 and 12.

The reference signal REF appears as a 500 nanosecond pulse which is generated by the 500 HZ voltage wave as the polarity of the voltage changes from positive to negative. The signal REF is used to reset the counters 38 and 39. The 500 HZ reference voltage provides the inputs to the resolvers 44 and 45 and the resolvers 44-47 are adjusted to have their outputs in phase with the coarse and fine command signals when the pin and the machine are at the end position 20 and the coarse and fine command counters 39 and 38 provide command signals of 500 HZ. Thus if a position equivalent to a count less than 500 is required, i.e., 250, the machine 10 will tend to move upstream. However, other switching circuits, not shown, will prevent the machine 10 from moving upstream beyond the position 20 so the machine 10 will wait at the end 20 until the pin 17 is moved the required 250 units distance into the work station. If the next required position requires a count of 350, the machine 10 will move downstream the required distance to satisfy the 350 count. Finally, if the next required position requires a count of 100, the machine 10will move upstream the required distance to satisfy the 100 count.

HOLD-JOG CIRCUIT Referring to FIGS. 1 and 4, the hold and jog circuit in FIG. 4 provides the functions included in the hold-jog module 34 and the switch module 61 and receives the l MHZ, the 500 KHZ and the 500 HZ reference input signals from the timing module 42. The switches H, JF, JR and FJ shown in FIG. 2 are included in the control module 32. The hold-jog circuit provides inputs F and R to the deceleration module 62 and inputs CCR and FCR to the coarse and the fine comparators 59-60. The circuit shown in FIG. 4 includes NANDS N21-N59, flip flops SS1-SS3, Fl-F4, CCR and FCR, Schmitt triggers STl and ST2, a timing module T, and a jog speed module 68.

During standby conditions, the hold switch H, the jog forward switch IF, the jog reverse switch JR and the fast jog switches F] are open, so that the NANDS N21, N37, N50, N56 and N43 respectively receive a 0 input and provide a 1 output. The flip flop SS1 is in an ON state and supplies a l at its E output and a O at itsEoutput. The l at the E output of the flip flop SS1 is supplied to an input of the NAND N22 which also receives a 1 input at its other two inputs in a manner which will be later described, so that the NAND N22 provides a 0 input to the NAND N23 and causes the NAND N23 to have a 1 output. The 1 output of the NAND N23 causes the NAND N24 to supply a 0 to the J input of the flip flop F1 and a 0 to the input of the NAND N25 so that the NAND N25 supplies a l to the K input of the flip flop F1 and the set input S of the flip flop F2. The flip flop F1 in response to the inputs at its J and K inputs supplies a 0 at its E output and a l at itsEoutput. The 0 at the E output of the flip flop F1 is supplied to the K inputs of the flip flops F3 and F4. The l at theEoutput'of the flip flop F1 is supplied to the K input of the flip flop F2 and as an input BC to the coarse and fine comparator circuits shown in FIG. 2. The l to the K input of the flip flop F2 causes the flip flop F2 to provide a l at its E output which is supplied to the inputs of the NANDS N32 and N33.

During standby conditions, the previously set flip flops CCR and FCR have a l at their respective E outputs which are respectively supplied through the NANDS N28 and N31 to the counters 39 and 38. The flip flops F3 and F4 in response to the 0 at their K in puts have a 0 at theirE outputs. The 0 at theE output of the flip flop E3 causes the NAND N26 to supply a 1 input to the NAND N27 so that the NAND N27 supplies a 0 to the K input of the flip flop CCR. The 0 at the E output of the flip flop F4 causes the NAND N29 to supply a 1 input to the NAND N30 so that the NAND N30 supplies a 0 to the K input of the flip flop FCR. The flip flop F3 receives the coarse feedback signal CFB at its toggle input T and the flip flop 'FCR receives the fine feedback signal FFB at its toggle T input. The 500 HZ signal is connected through the NAND N59 to supply inputs to the toggle inputs T of the flip flops F1 and F2. The 500 KHZ source supplies an input through a NAND N58 to the set inputs S of the flip flops CCR and FCR as well as an input 1 of the NANDS N26 and N29. The lMI-IZ source supplies an input through the NAND N57 to the toggle inputs T of the flip flops CCR and FCR so that the respective flip flops CCR and FCR supply outputs as described.

The hold period is initiated by closing the hold switch H so that a l is supplied to the input of the NAND N21. The NAND N21 has an output connected to the toggle input T of the flip flop SS1 which, together with the timing circuit T, is arranged to act as a single shot multivibrator. The 1 to change to the input T of the flip flop SS1 switches the flip flop SS1 so that a 0 appears at its E output, which causes the NAND N22 to switch, and provide a 1 output as input to the NAND N23. The l to 0 signal change from the NAND N21 to the input T of the flip flop SS1 also causes the flip flop SS1 to switch and supply a 0 to 1 signal change at its Eoutput, which change is delayed for 380 milliseconds and supplied by the timing circuit T as a l to 0 change to the set input S of the flip flop SS1. The 0 signal to the input S of the flip flop SS1 causes the flip flop SS1 to switch and again supply a l at its output E and a 0 at its output E, so that for 380 milliseconds after the hold switch H is closed, a 0 appears at the output E of the flip flop SS1. The 0 output of the NAND N23 is first inverted by the NAND N24 and supplied as a 1 to the J input of the flip flop F1 and again inverted by the NAND N25 and supplied as a 0 to the K input of the flip flop F1 and the S input of the flip flop F2. Flip flops F1 and F2 have their toggle inputs T connected through the NAND N59 to receive the 500 HZ signals so that at an appropriate 1 to 0 signal change at their inputs T, the flip flops F1 and F2 switch so that the flip flop Fl supplies a 1 at its E output and a 0 at its Eoutput. The l at the E output of the flip flop F1 is supplied to the inputs K of the flip flops F3 and F4 so that the flip flops F3 and F4 are conditioned to be switched upon a l to 0 change at their toggle T inputs. The 0 at the E input of the flip flop F1 is supplied to the K input of the flip flop F2 and as the signal BC to the comparators 59-60. The signal BC, which is supplied to the set inputs S of the flip flops FWD and REV and the NANDS N15 and N19 in the comparator circuits shown in FIG. 2, prevents the switching of the flip flops FWD, REV, FFWD and FREV to their OFF states and thus prevents the circuits within the comparators 59-60 from switching in response to the command signals and feedback signals. The flip flop F2 in response to the 0 at its S input supplies a 0 at its E output which causes the NANDS N32 and N33 to have a 1 output, the NANDS N34 and N35 to have a 0 output and the NAND N36 to have a 1 output. The output of the NANDS N35 and N36 are respectively supplied to the reverse and forward inputs R and F of the deceleration module 62 which, in response thereto, interrupts the energization of the motor 26 so that the motor 26 begins to coast to a stop. The motor 26 causes the rotation of the feedback resolvers 44 and 45. The resolvers 46 and 47 have their respective outputs connected to supply the toggle inputs T of the flip flops F3 and F4 with the coarse and the fine feedback signals CFB and FFB so that when the respective feedback signals CFB and FFB change from i to 0, the flip flops F3 and F4 switch ON and provide a l at their associated E outputs. The 1 at the E outputs of the flip flops F3 and F4 is supplied as an input to the NANDS N26 and N29 respectively. The NANDS N26 and N29 also receive an input through the NAND N58 from the 500 KHZ pulse source so that when the output of the NAND N58 changes from 0 to l, the NANDS N26 and N29 respectively will provide 0 inputs to the NANDS N27 and N and cause the NANDS N27 and N30 to switch and provide a 1 to the K inputs of the flip flops CCR and FCR. The 1 output of the NAND N58, which caused the NANDS N27 and N30 to have 1 outputs is also supplied as an input to the set inputs S of the flip flops CCR and FCR so that the flip flops CCR and FCR are conditioned to switch and supply a 0 at their associated E outputs upon a suitable 1 to 0 change from the lMHZ source through the NAND N57 at their associated inputs T which occurs 500 nanoseconds after the signal change at their set inputs S.

The 0 at the E outputs of the flip flops CCR and FCR, which are respectively supplied to the set inputs S of the flip flops F3 and F4, causes the flip flops F3and F4 to switch and again supply a O at their associated E outputs. The 0 at the Eoutputs of the flip flops F3 and F4 is respectively supplied to the K inputs of the flip flops CCR and FCR through the associated NANDS N26-N30. Thus 500 nanoseconds after the flip flops CCR and FCR are switched to supply a 0 at their associated E outputs, a signal change of 1 to 0 at the S input of the flip flops CCR and FCR from the 500 KHZ source through the NAND N58 causes the flip flops CCR and FCR to switch and again supply a l at the associated E outputs. Thus as the motor M coasts to stop, the counters 38 and 39 will be reset with a 0 pulse that has a 500 nanosecond duration each time the coarse and the fine feedback signals CFB and FFB respectively change from 1 to O, which occurs at a rate of 500 cycles per second or approximately times during the 380 millisecond interval as determined by the switching of the flip flop SS1.

As previously described, the single shot flip flop SS1 switches to provide a l at its E output 380 milliseconds after the switch H is closed. The 1 at the E output of the flip flop SS1 switches the NANDS N22-N25 so that the NAND N24 supplies a 0 to the J input of the flip flop F1 and the NAND N25 supplies a 1 to the input S of the flip flop F2 and a l to the input K of the flip flop F1 so that the flip flops F1 and F2 are conditioned to switch to their standby states upon the receipt of the suitable 1 to 0 at their inputs T from the 500 HZ source through the NAND N59. When the flip flops F1 and F2 are in their standby states, the E output of the flip flopFl is 0 and the E outputs of the flip flops F1 and F2 are l. The i 0 at the E output of the flip flop F1, which is supplied to the K inputs of the flip flops F3 and F4, causes the flip flops F3 and F4 to remain in their OFF states so that their E outputs are a continuous 0 in spite of the fact that the flip flops F3 and F4 are receiving a 1 to 0 signal change at their toggle inputs T from the feedback signals CFB and FFB. The 0 to 1 change at the E out-put of the flip flop F1, which is supplied to the input K of the flip flop F2, causes the flip flop F2 to switch to its standby state when the signal at its toggle input T from the NAND N59 changes from 1 m 0. The 1 at the E output of the flip flop F2 removes the blocking signal BC to the comparators 59-60 so that the operation of the circuitry within the comparators 59-60 is restored. The 1 signal at the E output of the flip flop F2, when the flip flop F2 is reset, permits the NANDS N32 and N33 to have a 0 output, the NANDS N34 and N35 to have a 1 output and the NAND N36 to have a 0 output so that the outputs of the NANDS N35 and N36 are in their standby condition.

The motor M may be caused to operate in a jogging mode either in the forward direction when the jog forward switch JF is closed, or in the reverse direction y when the jog reverse switch JR is closed. During standby conditions, that is, when both the switches JF and JR are open, the forward and reverse jog circuits will be conditioned as follows. The NAND N37 will have a input and supply a 1 output to the NAND N38 and the NAND N40. The NAND N38 is connected to the NAND N39 so that the NANDS N38 and N39 act as a NAND memory. The NAND N50 will have a 0 input and therefore supply a 1 input to the NANDS N51 and N40. The NAND N51 is connected to the NAND N52 so that the NANDS N51 and N52 act as a NAND memory. The NAND N40, during standby, has a 1 on all of its outputs and supplies a 0 to a circuit within a jog speed module 68. The 0 input to the module 68 causes the circuitry within the module 68 to supply a 1 input to the NAND N41 through a solid state Schmitt trigger STl and 0 input signal pulses to the NANDS N42 and N43 through a solid state Schmitt trigger ST2. The 1 input to the NAND N41 causes the NAND N41 to supply a O to the inputs of the NANDS N39 and N52 which switches the NAND memories so that the NANDS N38 and N51 have a 0 output and the NANDS N39 and N52 have a 1 output. The 1 output of the NANDS N39 and N52 are respectively supplied to a pair of inputs of the NAND N22 in the hold circuit which permits the NAND N22 to be switched in response to the l to 0 signal change from the E output of the flip flop SS1 when the switch H is closed, as previously described. The 0 outputs of the NANDS N38 and N51, which are respectively supplied as inputs to the NANDS N47 and N53, cause the NANDS N47 and N53 to have a 1 output. The output of the NAND N47 is supplied to an input of the NAND N48 which also receives a 1 input from the NAND N52 so that the NAND N48 supplies a 0 output which is inverted by the NAND N49 and supplied as a 1 input to the NAND N34. The 0 output of the NAND N51 causes the NAND N53 to have a 1 output which is supplied as an input to the NAND N54. The NAND N54 also receives a l at its other input from the NAND N39 so that the NAND N54 supplies a 0 input to the NAND N55 and causes the NAND N55 to supply a l as an input to the NAND N35. The comparators 59-60 have outputs F and R respectively connected as inputs to the NANDS N32 and N33. When positioning is not required, the outputs F and R of the comparators 59 and 60 are a continuous 1. Thus when positioning is not required and the jog switches JF and JR are open, all of the inputs of the NANDS N32 and N33 will be 1 and the NANDS N32 and N33 will provide a 0 output. When the motor 26 is to be rotated in the forward direction, the signal at the F output of the comparators 59-60 will be pulsed to O and cause the NAND N32 to provide a 1 output pulse. Similarly, when the motor 26 is to be rotated in a reverse direction, the signal at the R output of the comparators 59-60 will be pulsed to 0 and cause the NAND N33 to provide a 1 output pulse. When the NAND N32 has a 0 output, the output of the NAND N34 will be 1 and the output of the NAND N36 0, which is supplied to the F input of a deceleration module 62. When the NAND N33 has a 0 output, the NAND N35 will have a 1 output, which is supplied to the R input of the deceleration module 62. A switch in the output of the NAND N32 from the 0 to 1 will cause the output of the NAND N36 to switch from O to l and the deceleration module 62 to provide an output which will cause the motor 26 to operate in the forward direction. Similarly, a change in the output of the NAND N33 from 0 to 1 will cause the output of the NAND N35 to switch from 1 to 0 and the deceleration module 62 to provide an output which will cause the motor 26 to operate in the reverse direction. However, the circuitry within the deceleration module 62 is arranged so that when the inputs to the NANDS N32 and N33 are simultaneously 0, as occurs during the 380 milliseconds when the switch H is closed, the deceleration module 62 will not have an output which will cause the motor 26 to operate in either the forward or the reverse directions. The outputs of the NANDS N42 and N43 are respectively connected to the toggle inputs T of the flip flops SS2 and SS3. The flip flops SS2 and SS3 have their E outputs connected to supply an input to the NAND N46. The flip flop ssz has its E output connected through a time delay circuit consisting of an adjustable resistor R and a capacitor C to an input of the NAND N44 which in turn has its output connected to the set input S of the flip flop SS2. The flip flop SS3 has its E output connected through a time delay circuit consisting of an adjustable resistor R and capacitor C to an input of the NAND N45 which has its output connected to the set input S of the flip flop SS3. When the flip flops SS2 and SS3 are set, they respectively supply a 1 at their E outputs and a 0 at their E outputs. The NAND N46 in response to the 1 at the E outputs of the flip flops SS2 and SS3 provides a 0 input to the NANDS N47 and N53 which prevents the NANDS N47 and N53 from being switched when the outputs of the NANDS N38 and N51 become 1 as will be later described.

During intervals when the fast jog switch F] is open, the NANDS N56 and N43 have a 0 input and respectively supply a 1 input to the NAND N42 and the toggle 40 input T of the flip flop SS3. The 1 input to the NAND N42 from the NAND N56 permits the NAND N42 to be switched when the output signal pulses through the Schmitt trigger ST2 change to l. The 0 input to the NAND N43 prevents the NAND N43 from switching when the output pulses of the Schmitt trigger ST2 switches from O to 1. v

The motor 26 will be caused to operate in the jogging mode in the forward direction by closing switch JF so that the input to the NAND N37 changes from 0 to l and the NAND N37 provides a 0 output which causes the outputs of the NANDS N38 and N40 to become 1. The change in the output of the NAND N38 for a short time period after the switch JF is closed, Le, 50 milliseconds, does not cause any change in the remaining 55 portions of the circuit as the NAND N39 continues to receive a 0 input from the NAND N41 so its output remains 1 and the NAND N47 continues to receive a 0 input from the NAND N46 so its output remains l.

The circuitry within the jog speed module 68 is arranged so that approximately 50 milliseconds after the output of the NAND N40 changes from 0 to 1, the output of the Schmitt triggers STl and ST2 will respectively change so that the Schmitt trigger STl provides a continuous 0 output and the Schmitt trigger ST2 provides a pulsing 1 output. The 0 signal output of the Schmitt trigger STl is inverted by the NAND N41 and supplied as a 1 input to the NAND N39. As all of the in- 

1. A control circuit for comparing a feedback signal with a command signal during each cycle of a reference wave and providing an output error signal for controlling the speed of a motor in response to the difference in time of occurrence between a change from a first voltage level to a second voltage level of the feedback and the command signals and the direction of rotation of the motor in response to the order of occurrence of the voltage change of the feedback and the command signals, comprising: means including a first bistable state flip flop having a first input receiving the command signal and arranged to be switched from a first of its bistable states to a second of its bistable states by the change in the command signal when a logic 1 signal is present at a second of its inputs and arranged to remain in its first state when a logic 0 is presenT at its second input, means including a second bistable state flip flop having a first input receiving the feedback signal and arranged to be switched from the first of its bistable states to a second of its bistable states by the change in the feedback signal when a logic 1 signal is present at a second of its inputs and arranged to remain in its first state when a logic 0 is present at its second input, means responsive to the feedback signal for supplying the second input of the first flip flop with a logic 0 signal when the feedback signal is at the second voltage level and the second flip flop is in its first state, means responsive to the command signal for supplying the second input of the second flip flop with a logic 0 signal when the command signal is at the second voltage level and the first flip flop is in its first state, means responsive to an output of the first flip flop for causing the motor to be energized for rotation in one direction when the first flip flop is in its second state, means responsive to an output of the second flip flop for causing the motor to be energized for rotation in a direction opposite the said one direction when the flip flop is in its second state, and means including a third flip flop responsive to an output of the first flip flop and an output of the second flip flop for switching the first and the second flip flops to their respective first states when the first and the second flip flops are simultaneously in their second states.
 2. A control circuit for comparing a coarse feedback signal and a fine feedback signal respectively with a coarse command signal and a fine command signal during each cycle of a reference wave and providing an error signal for controlling the speed of a motor in response to the difference in time of occurrence between a change from a first voltage level to a second voltage level of the feedback and the command signals and the direction of rotation of the motor in response to the order of occurrence of the voltage change of the feedback and the command signals, comprising: means including a bistable state coarse command flip flop having an input responsive to the change in the coarse command signal to condition the flip flop so the flip flop is switched from its ON to its OFF state by an input signal at its toggle and an input responsive to the change in the coarse feedback signal for maintaining the flip flop in its ON state, means including a bistable state coarse feedback flip flop having an input responsive to the change in the coarse feedback signal to condition the flip flop so the flip flop is switched from its ON to its OFF state by an input signal at its toggle and an input responsive to the change in the coarse command signal for maintaining the flip flop in its ON state, timing means including a bistable state timing flip flop having an input responsive to the changes in the coarse feedback signal and the coarse command signal and an output providing the output signals to the toggles of the coarse command flip flop and the coarse feedback flip flop for switching the conditioned coarse command flip flop or the coarse feedback flip flop from their ON to OFF states a predetermined time interval subsequent to the change in the coarse command signal or the coarse feedback signal respectively when the interval between the occurrence of the changes in the coarse command and the coarse feedback signals is greater than the predetermined interval and for maintaining the coarse command flip flop and the coarse feedback flip flops in their respective ON states when the interval between the occurrence of the changes in the coarse command and the coarse feedback signals is less than the predetermined interval, a first control means responsive to an output of the coarse command flip flop for energizing the motor for rotation in a first direction at a pre-determined speed when the coarse command flip flop is in its OFF state, a second control means responsive to an ouTput of the coarse feedback flip flop for energizing the motor for rotation in a direction opposite the first direction at a predetermined speed when the coarse feedback flip flop is in its OFF state, and a fine feedback and fine command signal comparison means operable when the coarse command and the coarse feedback flip flops are in their ON states and responsive to the fine command and fine feedback signals for respectively supplying the first and the second control means with input signals which will cause the motor to rotate in a direction dependent upon the order of occurrence of the changes in the fine command and the fine feedback signals at a speed dependent upon the interval between the occurrence of the changes in the fine feedback and fine command signals.
 3. The control circuit as recited in claim 2 wherein the fine feedback and fine command signal comparison means includes: a first bistable state flip flop having a first input receiving the fine command signal and arranged to be switched from an ON state to an OFF state by the change in the fine command signal when a logic 1 signal is present at a second of its inputs and arranged to remain in its ON state when a logic 0 is present at its second input, a second bistable state flip flop having a first input receiving the fine feedback signal and arranged to be switched from its ON state to its OFF state by the change in the fine feedback signal when a logic 1 is present at a second of its inputs and arranged to remain in its ON state when a logic 0 is present at its second input, means responsive to the feedback signal for supplying the second input of the first flip flop with a logic 0 signal when the fine feedback signal is at the second voltage level and the second flip flop is in its ON state, means responsive to the fine command signal for supplying the second input of the second flip flop with a logic 0 signal when the fine command signal is at the second voltage level and the first flip flop is in its ON state, means responsive to an output of the first flip flop and supplying an input to the first control means for energizing the motor for rotation in the first direction when the first flip flop is in its OFF state, means responsive to an output of the second flip flop and supplying an input to the second control means for energizing the motor for rotation in the opposite direction when the second flip flop is in its OFF state, and means including a third flip flop responsive to an output of the first flip flop and an output of the second flip flop for switching the first and the second flip flops to their ON states when the first and the second flip flops are simultaneously in their OFF states.
 4. A circuit for controlling the speed, direction of rotation and deceleration of an electric motor in response to a train of constant frequency pulses at each of two terminals with the pulses at the first of the two terminals appearing as a logic 1 pulse which changes from a logic 0 and progressively decreases from a constant width to zero to cause the motor rotation in a first direction to be decreased from a constant speed to zero and the pulses at a second of the two terminals appearing as a logic 0 pulse which changes from a logic 1 and progressively decreases from a constant width to zero to cause the motor rotation in a second direction that is the reverse of the first direction to decrease from a constant speed to zero, comprising: a capacitor, means controlled by the train of pulses at the two terminals for maintaining the capacitor in a discharged state when the first and the second terminals are simultaneously 0 and 1 respectively and when the first and the second terminals are simultaneously 1 and 0 respectively and for causing the capacitor to be charged in a first direction with a current flowing in a first direction during periods when the first and the second terminals are simultanEously 1 and for causing the capacitor to be charged in a second direction with a current flowing in a second direction during periods when the first and the second terminals are simultaneously 0, and means including an operational amplifier having an input responsive to the direction of flow of the charging current and the total current energy required to charge the capacitor in response to the pulses appearing at the first and second terminals and providing an output for causing the motor to rotate in the first direction in response to the direction of the charging current flow at a speed proportional to the total current energy required to charge the capacitor in the first direction and for causing the motor to rotate in the second direction in response to the direction of the charging current flow at a speed proportional to the total current energy required to charge the capacitor in the second direction.
 5. The circuit as recited in claim 4 wherein the means for maintaining the capacitor in a discharged state and for causing the capacitor to be charged in a discharged state in response to the pulses at the two terminals includes: a junction, means including a pair of transistors respectively having their bases connected to the first and the second terminals for maintaining the junction at a common potential when the first and the second terminals are simultaneously 0 and 1 respectively and when the first and the second terminals are simultaneously 1 and 0 respectively and for causing the junction to have a first polarity during periods when the first and the second terminals are simultaneously 1 and a polarity opposite the first polarity when the first and second terminals are simultaneously 0, a means including a field effect transistor having a source and drain electrode connected across the capacitor and biased to a nonconductive state during periods when the first and second terminals are simultaneously 1 or 0, and means connecting the capacitor in a bidirectional charging circuit between the junction and the input of the operation amplifier.
 6. The circuit as recited in claim 4 wherein the means for maintaining the capacitor in the discharged state and for causing the capacitor to be charged in response to the pulses at the two terminals includes a pnp type transistor and a npn type transistor, said transistors having their collectors respectively connected through load resistors to a negative voltage source and a positive voltage source, their emitters connected to a terminal that is common to the negative and the positive voltage sources, and their bases respectively connected to the first and the second terminals, a field effect transistor having its source and drain electrodes connected across the capacitor, and a gate electrode arranged to bias the field effect transistor against conduction when the gate electrode is negative in polarity relative to its source and drain electrodes, a first voltage divider having two opposite ends respectively connected to the collectors of the npn transistor and the pnp transistor and a junction intermediate the ends providing a voltage potential equal to one half the potential across the opposite ends, a second voltage divider having two opposite ends respectively connected between the collector of the npn type transistor and the negative polarity source and a junction providing a potential that is negative relative to the collector of the pnp transistor when the npn and the pnp transistors are conducting, a potential that is positive relative to the collector of the pnp transistor when the pnp and the npn transistors are nonconducting, a potential that is positive relative to the collector of the pnp transistor when the pnp transistor is nonconducting and the npn transistor is conducting and a potential that is positive relative to the collector of the pnp transistor when the npn transistor is nonconducting and the pnp transistor is conducting, a second pnp type tranSistor having an emitter connected to the collector of the pnp transistor, a base connected to the junction of the second voltage divider and a collector connected to the gate of the field effect transistor and the negative polarity source, and a capacitor charging circuit connecting a first side of the capacitor to the junction of the first voltage divider and a second side of the capacitor to an input of the operational amplifier, said charging circuit including a pair of reversely poled diodes connected to cause the capacitor to be charged with current flow in one direction when the npn transistor is nonconducting and the pnp transistor is conducting and with current flow in a direction opposite the said one direction when the pnp transistor is nonconducting and the npn transistor is conducting. 